nand

module top;

wire a, A, b, B, c, C, d, D, F, F1, F2, F3, F4;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

nand S1(a, A, B);
nand S2(b, B, B);
nand S3(c, C, C);
nand S4(d, D, D);
nand C1(F4, A ,c , d);
nand C2(F2, a, b, D);
nand C3(F3, B, c, d);
nand C4(F1, C, D);
nand o1(F, F4, F2, F3, F1);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

期末考上機(練習)1

                                                                       
                                                                       module top;

wire A, B, C, D, F;
system_clock #1600 clock1(A);
system_clock #800 clock2(B);
system_clock #400 clock3(C);
system_clock #200 clock4(D);

not a(na, A);
not b(nb, B);
not c(nc, C);
not d(nd, D);
and a4(F4, A, nc, nd);
and a2(F2, na, nb, D);
and a3(F3, B, nc, nd);
and a1(F1, C, D);
or F(F, F4, F3, F2, F1);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

3位元加法器

module fulladder (sum, c_out, a, b, c_in);

wire s1, c1, c2;

output sum;

output c_out;

input a, b, c_in;

xor g1(s1, a, b);

xor g2(sum, s1, c_in);

and g3(c1, a,b);

and g4(c2, s1, c_in) ;

xor g5(c_out, c2, c1) ;

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c;

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;

fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;

fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

一位元全加法器

二位元多功器

1位元多工器 行為模式

4位元多功器