12/23 期末考

wire a, A, b, B, c, C, d, D, NF, F, F1, F2, F3, F4, F5;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

nor S1(a, A, A);
nor S2(b, B, B);
nor S3(c, C, C);
nor S4(d, D, D);
nor C1(F5, a, B, C);
nor C2(F4, a, C, D);
nor C3(F3, a, b, c, d);
nor C4(F2, A, b, C, d);
nor C5(F1, A, B, c);
nor o1(NF, F5, F4, F2, F3, F1);
nor o2(F, NF, NF);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

nor

module top;

wire a, A, b, B, c, C, d, D, NF, F, F1, F2, F3, F4;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

nor S1(a, A, A);
nor S2(b, B, B);
nor S3(c, C, C);
nor S4(d, D, D);
nor C1(F4, a ,C , D);
nor C2(F2, A, B, d);
nor C3(F3, b, C, D);
nor C4(F1, c, d);
nor o1(NF, F4, F2, F3, F1);
nor o2(F, NF, NF);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

nand

module top;

wire a, A, b, B, c, C, d, D, F, F1, F2, F3, F4;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

nand S1(a, A, B);
nand S2(b, B, B);
nand S3(c, C, C);
nand S4(d, D, D);
nand C1(F4, A ,c , d);
nand C2(F2, a, b, D);
nand C3(F3, B, c, d);
nand C4(F1, C, D);
nand o1(F, F4, F2, F3, F1);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

期末考上機(練習)1

                                                                       
                                                                       module top;

wire A, B, C, D, F;
system_clock #1600 clock1(A);
system_clock #800 clock2(B);
system_clock #400 clock3(C);
system_clock #200 clock4(D);

not a(na, A);
not b(nb, B);
not c(nc, C);
not d(nd, D);
and a4(F4, A, nc, nd);
and a2(F2, na, nb, D);
and a3(F3, B, nc, nd);
and a1(F1, C, D);
or F(F, F4, F3, F2, F1);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule